This circuit adds the proper increments to the Row, Column and Refresh Registers and generates signals indicating End-of-Line and End-of-Frame in the OpticRAM.
When any of the Address Registers drive a value onto the Present Address bus, the Adder circuit receives this value, adds a 0, 1 or 2 to it (depending on the control inputs) and drives the sum onto the Next Address bus. The control lines are RASP, LINE, ALTBIT and INT. When the Refresh Register is active, the INT line causes a "1" to be added each cycle. During interrupt cycles, the Row and Column Registers are active. The Adder sequences these registers through the OpticRAM in a column-fast mode, i.e., the Adder adds a "zero" to the Row Address and a "one" to the Column Address until the end of the column (End-of-Line) is reached. the Adder then adds a 1 to both the Row and Column, thus incrementing the Row Register and resetting the Column Resister to zero.
The ALTBIT input simply adds another "1" to the value on the Present Address bus during Interrupt cycles,, thus the Row and Column Reigsters are incremented by 2 rather than 1.
During Refresh cycles, the INT signal is low, forcing the Carry In input to the Adder (C1-13) to be high. Thus, a value of "1" is added to the value on the Present Address bus on each Refresh cycle.
During Interrupt cycles, the INT signal is high. Let's assume LINE and ALTBIT are low. For the first half of the Interrupt cycle, the Row Register is active and RASP is high, forcing the Carry-In input of the Adder to be low. A zero is added to the Present Address value, so the Row Register address remains unchanged.
When RAS goes low, the Column Register is active and a high is driven onto the Adders Carry-In input. A "1" is added to the Present Address bus and the incremented value is stored back into the Column Register. Thus, the Registers count down the columns in the same row.
When the last cell is acessed, the Column Address is at the Adder's terminal count of 255, setting the carry- out signal high. (The Column Register is incremented to zero). The high Carry-Out sianal is latched by the rising edge of INT/ at F1-2, and forces the outputs, LINE and LINE/ (F1-5 and 6) to the asserted state. These signals cause the next Interrupt cycle to occur during the transmission of the next stop bit. The LINE input to the Exclusive-OR at E1-2, reverses the effect of RASP on the Adders' Carry-In input. Thus, a "1" is added to the Row Register and a "O" is added to the Column Register. The pixel that is accessed during this Interrupt is blanked by the stop bit transmission. At the start of the next Interrupt cycle (when RASP goes high), LINE and LINE/ are reset and the circuit sequences down this next row.
Let's assume the last pixel in the opticRAM has been accessed and LINE has been set. The Column Register has been incremented to zero and the Row Register is at terminal count (255). The next Interrupt cycle forces the Pow Register to drive its value of 255 onto the Present Address bus and to the Adder. The Adder adds a "1" to it and drives a value of zero onto the Next Address bus and also sets the Carry-Out (C5-14) high. The Carry-Out and LINE signals force the output of the AND gate (B2-11) high, thus setting the flip-flop input (E4-2) high also. When RASP goes low, the NCR gate (B3-10) goes high, clocking E4-3. The Q./ output of the flip-flop (E4-6) goes low. This is the End-of-Frame signal. The EOF is connected to the reset input of the Command Register, so a low on the EOF line resets all of the command lines to zero. The XMIT command line is connected to the flip-flop reset (E4- 1), so when XMIT goes low, flip-flop E4-1 is reset and the EOF signal is reset high. Note that the Row and Column Registers both now hold a value of zero.