This circuit latches the Row, Column and Refresh pointers for the OpticRAM addressing.

General Description

Address registers C4 and C3 hold the PAS and CAS addresses, respectively. These registers are enabled only when the camera is to fetch and transmit a single bit of information from the opticRAM. This fetch operation is initiated by the INT signal going high, and is called an Interrupt cycle. An Interrupt cycle is started on the rising edge of RASP and is ended on the next rising edge of RAS'.When the camera is not in an Interrupt cycle, the Refresh Register, C2, is active. This register increments the Row Address from O to 255, thus performing a refresh operation on the OpticRAM. All three Registers have tri-state outputs and only one register is active at any one time. The selected register drives its data onto a common bus called the Present Address bus. The Present Address passes through the descramble and soak circuitry, to the OpticRAM, where it is used to select a Row or Column. The Present Address bus also connects to the Address Circuit, where a value of 0, 1 or 2 is added to the Present Address value. The resulting sum is driven out of the adder onto the Next Address bus. This bus connects to the inputs of each of the Address Registers. The value on the Next Address bus is latched into the selected Address Register and then that Register is disabled.

Circuit Description

When the MicronEye is not in an Interrupt mode, the INT signal is low and the INT/ signal is high. this forces the Enable inputs (active low) to C3 and C4 to remain high. When RASP and Td go high and INT is high, the NAND gate output at A1-3 is low, enabling C2. C2 drives its data onto the Present Address bus. The data propagates to the OpticRAM and to the Adder circuit. The Adder circuit adds a 1 to the value on the Present Address bus and drives the sum onto the Next Address bus where it appears at the inputs to C2. When RASP goes low, the descrambled Present Address is latched into the OpticRAM, and the output of A1- 3 goes high, clocking the value on the Next Address bus into C2 and turning off the outputs.

During an Interrupt cycle, INT/ is low, so C2 is disabled. The rising edge of RASP initiates the Interrupt cycle, so initially RASP (and Td) and INT will be high, driving the NAND gate A1-8 low and enabling the Row Register, C4. C4 drives its value onto the Present Address bus. Some value, either 0,1 or 2 is added to it in the Adder and the sum is placed on the Next Address bus. When RASP goes low, the Next Address value is latched into the Row Register, the Row Register outputs are disabled and the Column Registers outputs are enabled. The data from the Column Register, C3, is driven onto the Present Address bus, through the Adder Circuit (where it may be incremented) and onto the Next Address bus. It also propagates to the OpticRAM where it is latched when CAS goes low. When RASP goes high, the value on the Next Address bus is latched into the Column Register and it's output drivers are disabled.

The Array Selection circuit determines whether one or both arrays are transmitted. If 2APRAY/ is high, the output of the OR gate (B4-11) is always high and the Row Register value (C4) will never be less than 128. Thus, only the second array (rows 128 to 255) will be addressed. If 2ARRAY/ is low, however, the OR gate will appear transparent and the value on the Next Address bus line D7 will drive onto C4. This means all addresses from 0 to 255 will be selected and both arrays will be transmitted.