This circuit transmits the serial information, inserting start and stop bits where appropriate, and generates the INT and INT/ signals for fetching pixel information.

At the heart of this circuit is the ripple Counter, D1. D1 is enabled when the MicronEye has been commanded to transmit data. It inhibits the Interrupt circuit when start and stop bits are being transmitted, and enables the Interrupt circuit when it is transmitting data. The Transmitter is clocked by the baud clock. On each baud clock cycle, only one start, stop or data bit is transmitted.

The Interrupt Generator is enabled by both the ripple counter (D1) and the baud clock, but the Interrupt cycle is clocked by RASP. Remember the purpose of the Interrupt cycle is to fetch a single pixel for transmission, and only one pixel can be tansmitted on each baud clock cycle. The rising edge of the baud clock enables the Interrupt circuit. The next rising edge of RAS initiates the Interrupt cycle, causing a pixel to be read from the OpticRAli. The INT/ signal feeds back into the Interrupt circuit, resetting the Interrupt enable. When PAS' goes high again, the Interrupt cycle is terminated. The next rising edge of the baud clock will enable the Interrupt circuit again (unless a start or stop bit is to be transmitted). Thus, only one pixel is transmitted during each baud clock cycle.

The WIDEPIX circuit is used to help compensate for the 2.5 to 1 aspect ratio of the OpticRAM. If the optic data is displayed on a screen with a 1 to 1 aspect ratio, the image will appear to be squeezed in the horizontal direction. The WIDEPIX circuit helps compensate for this by causing each pixel to be transmitted twice, doubling the width of the image. The circuit is enabled when the MicronEye is transmitting and the WIDEPIX command bit is high. This causes the flip-flop output A2-5 to toggle on every baud clock cycle.

This flip-flop inhibits the Interrupt cycle on alternate baud clock cycles. During baud clock cycles in which the Interrupt is inhibited, the pixel from the previous Interrupt cycle is transmitted again.

When the MicronEye is not in a Transmit mode, the XMIT signal is low, driving the ripple counter RESET input high (01-15). This puts the ripple counter in a reset state in which output Q0 (D1-3) is high. The high on Q0 drives the RESET input at E5-1, low and the flip-flop Q./ output E5- 6, high. E5-6 is the data transmission line to the computer. The high level of Q0 (D1-3) also drives the flip- flop data input (E5-12) high (let's assume LINE is low). This prevents any Interrupt cycles from occuring.

When the MicronEye receives a Transmit command, XMIT goes high, XMIT/ goes low and the ripple counter D1 is enabled. D1 is clocked by the rising edge of the BAUD clock. The first clock causes Q0 (D1-3) to go low and Q1 (D1-2) to go high. This sets the transmit line E5-6 low, representing the start bit. The first clock also forces a high at flip-flop data input, E5-12. The baud clock is delayed through an RC network (R3 and C2) and now clocks the high input at flip-flop E5-12 to the output at E5-9. This forces a high on the input of the Interrupt flip- flop, A2-12. When RASP goes high at the flip-flop clock input A2-11, it initiates the Interrupt cycle. INT goes high and INT/ goes low. INT/ is an input to the AND gate. B2-1 and forces the flip-flop RESET inputs (E5-13) low. This forces A2-12 low, so on the next rising edge of RASP, the Interrupt cycle is terminated. INT/ going high clears the RESET at e%-13 and another interrupt will occur when the baud clock goes high again.

When the WIDEPIX bit is set high, the RESET input at A2-1 is high, enabling the flip-flop. The output toggles on each interrupt request and inhibits every other interrupt cycle by bringing the RESET input A2-13 low.

The LINE and LINE/ signals indicate that the Column Address Register has reached terminal count. These signals inhibit further interrupts from occurring during data bit transmissions, so the value of the last accessed data bit is repeated to complete the current byte transmission. This guarantees that the next byte transmitted contains information from the next row, i.e., no single byte will contain information from two rows. When the stop bit is to be transmitted, LINE at E1-5 causes an Interrupt Request and LINE/ at A1-4 ensures that the Interrupt flip-flop is enabled. This "dummy" interrupt is used to increment the Row Address Register. The pixel that is accessed during this cycle is blanked by the transmission of the Stop bit.