This circuit generates the timing signals for the operation of the MicronEye. A CMOS oscillator circuit generates the basic clock signal. This signal is divided down to produce the various possible baud rates and the timing signals which drive the IS32. The baud clock signals sequence the Interrupt Generator and the Transmitter circuit.

The oscillator circuit consists of a CMOS inverter, a crystal, two resistors and two capacitors. It generates a 4.9152 Mhz signal which is buffered by an inverter (A4,pin2). Thiq frequency is divided in half by a D flip-flop at A3-5, and again at A3,pin9. Both outputs lead to baud rate selection pads. Flip-flop output A3,pin 9 also connects to the clock input at B5,pin10. IC B5 does successive frequency divide-by-twos. The various outputs lead to other baud rate selection pads. Pads 5 through 8 are baud Clock signals. One of these baud clocks is used in the transmitter and Interrupt Generator circuit. Pads 1 through 4 are clock signals that are 16 times higher in frequency than the baud clocks. One of these 16x clock signals is used in the receiver circuit.

The output of B5,pin7 drives the Optic RAM timing circuitry which generates RAS, CAS and R/W (read/write). The outputs of inverters A4,pin4 and A4,pin6 are identical. A4,pin4 drives the RAS input to the Optic Ram, and is buffered separately because it is required to drive its signal through the ribbon cable if a Bullet MicronEye is used. A4,pin 6 is identical to the RAS signal, but it is used as inputs to other camera circuitry and is labeled RAS'.

When the camera is not in an Interrupt mode (i.e., is not transmitting data from the OpticRAM), CAS and R/W are disabled. The signal INT is low and INT/ (The "/" after a signal name indicates the complement of the signal.) is high, so the AND gate driving CAS remains low and the OR gate driving R/W remains high.

During an Interrupt cycle, INT goes high and INT/ goes low, enabling CAS and R/W. RAS' goes low with RAS which latches the Row address into the Optical. RAS' passes through a delay line consisting of 2 inverters and an RC network, and then causes CAS to go low, latching the Column Address into the OpticRAM. At this time the R/W signal is still high, so the accessed pixel is read out. After another delay period, R/W goes low, which causes the OpticRAM to write data into the accessed cell. The addressing circuitry presents the proper data on the Data In pin to make sure that 5 volts is written back into the cell.

When RAS' goes high, the Interrupt cycle is terminated and CAS and R/W are disabled.